Semiconductor memory system

ABSTRACT

A semiconductor memory system includes: a memory cell array having a plurality of memory cells arranged therein, the plurality of memory cells capable of storing N bits of information in each memory cell (where N is a natural number more than 3, other than a power of two); a control circuit configured to control read, write, and erase operations on the memory cell array; and an ECC circuit configured to correct data read from the memory cell array, based on redundant data. The memory cells that share one of word lines and can be written or read at a time are configured to store multiple pages of data therein. A total amount of data stored in the multiple pages is set to a power-of-two number of bits, and the redundant data is stored in a residual portion of the multiple pages.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2008-249531, filed on Sep. 29,2008, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a non-volatile semiconductor storagesystem, and particularly, to a nonvolatile semiconductor storage deviceenabled to store multiple bits in one memory cell.

2. Description of the Related Art

One of the well-known non-volatile semiconductor storage systems is aNAND cell type flash memory. The NAND cell type flash memory includes amemory cell array including a plurality of NAND cell units. Each NANDcell unit includes a plurality of memory cells connected in series andtwo selection transistors connected to both ends thereof.

The memory cell holds, in an erase state, data “1” and has a negativethreshold voltage. In a data write operation, a floating gate of thememory cell is injected with electrons to write data “0”, and the memorycell has a positive threshold voltage. The NAND cell type flash memorymay change the threshold voltage of the memory cell only from a lowervalue to a higher value in a data write operation, and may change thethreshold voltage in the reverse direction (from a higher value to alower value) only by an erase operation per block.

To increase memory capacity, current developments are directed to aso-called multi-value NAND cell type flash memory that stores two ormore bits of information in one memory cell. For example, when 3 bitsare stored in one memory cell, one memory cell involves 2³=8 differentthreshold voltage distributions (see, for example, Japanese PatentLaid-Open No. 2008-077810).

Meanwhile, since the NAND cell type flash memory is usually controlledin a unit of power-of-two bits of data, host devices utilizing such theNAND cell type flash memory are also designed for data control in a unitof power-of-two bits of data.

However, in the NAND cell type flash memory where 3 bits are stored inone memory cell, for example, the amount of data that is subject todata-erase at a time in a data erase unit (block) is not a power-of-twobits of data. As such, there may be a mismatch (discrepancy) between thelogic block size of a host device and the data erase unit of the NANDcell type flash memory. Consequently, such situations frequently arisewhere data copy operations are required within the system, causingadditional overhead in the system. This may result in serious disruptionto normal operation in some applications, such as video recording thatrequires data write/read to be performed in a continuous manner. Thisissue may arise not only when performing multi-value storage of 3 bitsper cell, but also when performing that of N bits per cell (where N is anatural number more than 3, other than a power of two).

SUMMARY OF THE INVENTION

One aspect of the present invention provides a semiconductor memorysystem comprising: a memory cell array having a plurality of memorycells arranged therein, the plurality of memory cells capable of storingN bits of information in each memory cell (where N is a natural numbermore than 3, other than a power of two) ; a control circuit configuredto control read, write, and erase operations on the memory cell array;and an ECC circuit configured to correct data read from the memory cellarray, based on redundant data, the memory cells that share one of wordlines and can be written or read at a time being configured to storemultiple pages of data therein, a total amount of data stored in themultiple pages being set to a power-of-two number of bits, and theredundant data being stored in a residual portion of the multiple pages.

Another aspect of the present invention provides a semiconductor memorysystem comprising: a memory cell array having a plurality of memorycells arranged therein, the plurality of memory cells capable of storingN bits of information in each memory cell (where N is a natural numbermore than 3, other than a power of two); and a control circuitconfigured to control read, write, and erase operations on the memorycell array, the memory cell array comprising: a binary memory regionconfigured to store 1 bit of information in one of the memory cells; anda multi-value memory region formed to store the N bits of information inone of the memory cells, the control circuit being operative to store inthe binary memory region data supplied from outside in a unit of datawith a power-of-two number of bits to be written to the memory cellarray, and then sequentially transfer the data stored in the binarymemory region to the multi-value memory region; the memory cells thatshare one of word lines and can be written or read at a time beingconfigured to store multiple pages of data therein; and a total amountof data stored in the multiple pages being set to a power-of-two numberof bits, and the redundant data being stored in a residual portion ofthe multiple pages.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a general configuration of a memory card 20, whichrepresents a non-volatile memory system according to a first embodimentof the invention;

FIG. 2 is illustrates a configuration of functional blocks where a logiccontrol is described in an integrated manner for the memory chip 21 andthe controller 22 of the memory card 20 of FIG. 1;

FIG. 3 is a circuit diagram illustrating a specific configuration of thememory cell array 1;

FIG. 4 is a cross-sectional view illustrating a configuration of onememory cell MC;

FIG. 5 is a cross-sectional view illustrating a configuration ofselection transistors S1 and S2;

FIG. 6 is a cross-sectional view illustrating a configuration of oneNAND cell unit NU;

FIG. 7 illustrates the states of threshold voltage distributions (therelation between the threshold voltage Vth and the number of cells)where 3 bits of information are stored in one memory cell;

FIG. 8 is a schematic diagram illustrating a method of storing data inthe memory cell array 1 of the first embodiment;

FIG. 9 is a schematic diagram illustrating a method of storing data in amemory cell array 1 according to a second embodiment;

FIG. 10 is a schematic diagram illustrating a method of storing data ina memory cell array 1 according to a third embodiment;

FIG. 11 is a schematic diagram illustrating a method of storing data ina memory cell array 1 according to a fourth embodiment; and

FIG. 12 is a schematic diagram illustrating a method of storing data ina memory cell array 1 according to a variation of the fourth embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention will now be described in detailbelow with reference to the accompanying drawings.

First Embodiment

Referring first to FIG. 1 and the like, a non-volatile memory systemaccording to a first embodiment of the present invention will bedescribed below.

[System Overview]

FIG. 1 illustrates a general configuration of a memory card 20, whichrepresents the non-volatile memory system according to the firstembodiment of the invention. The memory card 20 configures modules witha NAND-type flash memory chip 21 and a memory controller 22. The memorycontroller 22 controls reading/writing from/to the NAND-type flashmemory chip 21.

The flash memory chip 21 may be a plurality of memory chips. AlthoughFIG. 1 illustrates two memory chips, i.e., chip 1 and chip 2, these arealso controlled by the single memory controller 22. The memorycontroller 22 is a one-chip controller that has a NAND flash interface23, a host interface 25, a buffer RAM 26, an MPU 24, and a hardwaresequencer 27. The NAND flash interface 23 is used for transferring datato and from the memory chip 21. The host interface 25 is used fortransferring data to and from a host device. The buffer RAM 26 is usedfor temporarily retaining read/write data, etc. The MPU 24 is used forcontrolling, not only data transfer, but also entire operations in thememory card. The hardware sequencer 27 is used for e.g., sequencecontrol of read/write of firmware (FW) within the NAND-type flash memory21.

When the memory card 20 is powered on, an initializing operation(power-on initial setup operation) is performed to automatically readfirmware (control program) stored in the flash memory 21, which in turnis transferred to the data register (buffer RAM) 26. This read controloperation is performed by the hardware sequencer 27.

Using the firmware loaded on the buffer RAM 26, the MPU 24 createstables on the RAM 26, accesses the flash memory 21 in response tocommands from the host, controls data transfer, and so on. In addition,the NAND flash interface 23 comprises an ECC circuit for performingerror correction on effective data that is stored in the flash memorychip 21, based on redundant data that is also stored in the flash memorychip 21. As described below, the ECC circuit is configured to performerror correction in a unit of three pages of data that are stored inmemory cells MC (3 bits per cell) formed along one word line WL, ratherthan performing it in a unit of one page.

However, it is not essential for the present memory system that thememory chip 21 and the controller chip 22 are separate chips. FIG. 2illustrates a configuration of functional blocks of the memory card 20,where a logic control of the memory chip 21 and the controller 22 isillustrated in an integrated manner. In addition, FIG. 3 illustrates aconfiguration of a cell array in a memory core portion.

As illustrated in FIG. 3, a memory cell array 1 includes NAND cell units(NAND strings) NU arranged therein, each of which has a plurality ofelectrically rewritable non-volatile memory cells (in FIG. 3, 64 memorycells) M0-M63 connected in series. A power-of-two number+α, e.g., 16k+αpieces of such NAND cell units NU together form one block BLK, sharingthe corresponding word lines WL.

Among 16k+α, 16k NAND cell units NU are mainly used for storingeffective data supplied from an external host device, while theremaining α NAND cell units are provided for storing redundant data andmanagement flags for error correction.

One block BLK forms one unit for data erase operation. In addition, when3 bits of data are stored in one memory cell MC (3 bits per cell), threepages (upper page UPPER, middle page MIDDLE, and lower page LOWER) ofdata are stored by memory cells MC that are formed along one word lineWL. In this embodiment, the number of bits of effective data to bestored in one page is controlled so that three pages of data stored inthe memory cells MC along one word line WL and capable of being writtenor read at a time correspond to power-of-two bits of effective data (thenumber of bits of effective data in each page is not power of two bits).This is described in greater detail below.

The number of word lines WL included in one block in one memory cellarray 1 is 64, and the number of pages included in one block is64×3=192.

Given that the number of memory cells MC (the number of bit lines BL)along one word line WL is 16k+α, each block in one memory cell array 1has a capacity of 64×16k×3=3 Mbits (in the case of storing 3 bits ineach memory cell).

In addition, the memory cell array 1 of this embodiment comprises amulti-value memory region (MLC) 1 a for storing multi-value data and abinary memory region (SLC) 1 b for storing binary data. It is, however,also possible to form only the multi-value memory region 1 a, omittingthe binary memory region 1 b.

As illustrated in FIG. 3, one end of each of the NAND cell units NU isconnected via a selection gate transistor S1 to a respective bit lineBL, and the other end connected via a selection gate transistor S2 to acommon source line CELSRC. The control gates of the memory cells M0 toM63 are connected to respective word lines WL0-WL31. The gates of theselection gate transistors S1, S2 are connected to respectiveselection-gate lines SGD, SGS.

A sense amplifier circuit 3 a, which is utilized to read and write celldata, is positioned at one end of each of the bit lines BL, and a rowdecoder 2 (not illustrated in FIG. 3), which selectively drives eachword line and selection-gate line, is positioned at one end of each ofthe word lines WL.

Commands, addresses and data are input via an input control circuit 13.Chip-enable signals/CE, write-enable signals/WE, read-enable signals/RE,and other external control signals are input to a logic circuit 14 fortiming control. Commands are decoded at a command register 8.

A control circuit 6 controls data transfer and performs write/erase/readsequence control. A status register 11 outputs Ready/Busy states of thememory card 20 to a Ready/Busy terminal. In addition to this, a statusregister 12 is also provided that informs the host of the states of thememory 20 (Pass/Fail, Ready/Busy, etc.) via an I/O port.

Addresses are transferred via an address register 5 to the row decoder 2(including a pre row decoder 2 a and a main row decoder 2 b) or a columndecoder 4. Write data is loaded via an I/O control circuit 13 throughthe control circuit 6 to the sense amplifier circuit 3 (including asense amplifier 3 a and a data register 3 b), while read data is outputvia the control circuit 6 to the outside.

A high-voltage generation circuit 10 is provided for producing a highvoltage required for each mode of operation. The high-voltage generationcircuit 10 produces a predetermined high voltage based on orders fromthe control circuit 6.

FIGS. 4 and 5 illustrate cross-sectional structures of one memory cellMC as well as selection gates S1 and S2, respectively. FIG. 4illustrates a cross-sectional structure of one memory cell MC. N-typediffusion layers 42 are formed on a substrate 41, and function as thesource and drain of MOSFET included in the memory cell MC. In addition,a floating gate (FG) 44 is formed on the substrate 41 via a gateinsulation film 43. A control gate (CG) 46 is formed on the floatinggate 44 via an insulation film 45.

Each of the selection gates S1 and S2 comprises the substrate 41 andn-type diffusion layers 47 formed on the substrate 41 as its source anddrain. A control gate 49 is formed on the substrate 41 via a gateinsulation film 48.

FIG. 6 illustrates a cross section of one NAND cell of the memory cellarray. In this example, one NAND cell includes 64 memory cells MCconfigured as illustrated in FIG. 4, which memory cells are connected inseries. Provided at the drain and source sides of the NAND cell are afirst selection gate S1 and a second selection gate S2 configured asillustrated in FIG. 5.

A multi-value storage operation will be described below that isperformed in the NAND cell type flash memory so configured according tothis embodiment. In the NAND cell type flash memory according to thisembodiment of the present invention, the value of threshold voltage iscontrolled in eight different ways for one memory cell to cause 3 bitsof data to be stored in one memory cell.

FIG. 7 illustrates threshold voltage distributions (the relation betweenthe threshold voltage Vth and the number of cells) where 3 bits ofinformation are stored in one memory cell. To store 3 bits ofinformation, eight different threshold voltages are providedcorresponding to eight different states of “111”, “011”, “001”, “101”,“100”, “000”, “010” and “110” for writing and reading information. Threesub-pages are formed for the 3 bits: upper page UPPER, middle pageMIDDLE, and lower page LOWER.

Furthermore, corresponding to the eight different threshold voltagedistributions, the voltage values of read voltage to be applied to aselected word line in read operation may be set to voltages R1, R2, R3,R4, R5, R6 and R7 (seven different voltages) between the thresholdvoltage distributions. Note that a voltage Vread to be applied to anunselected memory cell in read operation is set to be greater than thevoltage of the threshold voltage distribution in state “110”.

In addition, voltage values at the time of verify operation for checkingthe completion of information write may be set to VR1, VR2, VR3, VR4,VR5, VR6, and VR7 that are greater than the above-mentioned voltages.

Referring now to the schematic diagram of FIG. 8, a method of storingdata in the memory cell array 1 of the first embodiment will bedescribed below. As described above, one memory cell MC can store 3 bitsof data, and the number of memory cells MC formed along one word line WLis generally a power-of-two number, e.g., 16k+α, 16k plus α for storingredundant data.

However, when 3 bits of data are stored in every such 16k+α memory cellMC along one word line WL, the amount of data (effective data) that canbe stored in the memory cells MC along one word line WL is 16 Kbits×3bits=48 Kbits .

However, the resulting 48 Kbits does not correspond to a power-of-twonumber. Thus, there may be a mismatch with the host device treatingpower-of-two bits of data as a unit when 48 Kbits of data are written tothe memory cells MC along one word line WL (3 bits per cell).

As such, in this embodiment, the number of bits (amount) of data (threepages of data) stored in those memory cells MC sharing one word line WLand configured to be read or written at a time is set to 32 Kbits+AKbits. Note that 32 Kbits is a power-of-two bits, which is smaller than48 Kbits. In addition, A Kbits represents the number of bits ofredundant data and management flags for use in error correction. If suchsetting is done, and error correction is performed in a unit of thethree pages along one word line WL, the unit of data in the memory 21may be consistent with that in the external host device.

On the other hand, the capacity of each page (page size) is set to 11Kbits+α Kbits, which is slightly larger than one-third of 32 Kbitsmentioned above. Where A=3α Kbits+1 Kbits. The difference between 11Kbits×3=33 Kbits and 32 Kbits, i.e., 1 Kbits are used for storingredundant data. That is, 1 Kbits+3α Kbits are prepared for redundantdata and management flags for each word line WL. In other words, theamount of redundant data for error correction of three pages of data isset to be larger than 1 Kbits.

As can be seen, while 11 Kbits for each page involved in the memorycells MC formed along one word line is not a power-of-two bits, there isno problem if the number of bits of data to be stored in each page isnot a power of two because the ECC circuit performs error correction forevery three pages of data, as described above. Stored in the residualportion in one page is redundant data for use in error correction ofeffective data.

Second Embodiment

Referring now to FIG. 9, a second embodiment of the present inventionwill be described below.

According to this embodiment, although the entire configuration of thesemiconductor storage device is substantially the same as the firstembodiment (see FIGS. 1 to 6), the data transfer procedure (scheme) ofmulti-value storage operation is different from the first embodiment.Thus, in the following, the data transfer procedure will be describedwith reference to FIG. 9, and the description of other configurationwill be omitted.

This embodiment is different from the first embodiment in that data(effective data) supplied from the external host device in a unit ofpower-of-two number of bits (e.g., 512 bits, 1 Kbits, 2 Kbits, and soon) is first written to the binary memory region 1 b, and then convertedinto three pages of data, which in turn are rewritten (transferred) tothe multi-value memory region 1 a. For example, effective data isreceived in 8 Kbits, which 8 Kbits of effective data are written to thebinary memory region 1 b with α Kbits of redundant data being addedthereto. The binary memory region 1 b is divided into a plurality ofbinary memory regions 1 b-1 to 1 b-4 (unit storage regions).

If the effective data stored in the binary memory regions 1 b-1 to 1 b-4exceeds 32 Kbits, then the data written to the binary memory regions 1b-1 to 1 b-4 is transferred again to the buffer RAM 26 in the memorycontroller 22, and then allocated to the three pages along one word lineWL (upper page UPPER, middle page MIDDLE, and lower page LOWER).

For example, the 8 Kbits of data that are stored in the binary memoryregion 1 b-1 will all be allocated to the lower page LOWER. Theredundant data and management flags as well as some of 8 bits of datastored in the memory region 1 b-2 are allocated to the residual portionof the lower page LOWER. In this way, 11 Kbits of effective data (inthis case, 8 Kbits from the memory region 1 b-1 and 3 Kbits from 1 b-2)and α Kbits of redundant data and management flags are stored in thelower page LOWER.

In addition, excess data (in this case, 5 Kbits) from the memory region1 b-2 that may not be stored in the lower page LOWER is stored in themiddle page MIDDLE. Furthermore, redundant data and management flags aswell as some of 8 bits of data (in this case, 6 Kbits) stored in thememory region 1 b-3 are allocated to the residual portion of the middlepage MIDDLE. In this way, 11 Kbits of effective data and α Kbits ofredundant data and management flags are stored in the middle pageMIDDLE.

In addition, excess data (in this case, 2 Kbits) from the memory region1 b-3 that may not be stored in the middle page MIDDLE is stored in theupper page UPPER. Furthermore, redundant data and management flags aswell as 8 bits of data stored in the memory region 1 b-4 are allocatedto the residual portion of the upper page UPPER. In this way, 10 Kbitsof effective data and α Kbits of redundant data and management flags arestored in the upper page UPPER.

As such although, each of the lower page LOWER, the middle page MIDDLE,and the upper page UPPER stores data that is not power-of-two bits (11Kbits, or 10 Kbits), these three pages in total store 32 Kbits of datawhich corresponds to power-of-two bits of data. Therefore, the datamanagement unit in the memory 21 is matched with that of the externalhost device, providing the same advantages as the first embodiment. Itshould be appreciated that while the description has been made in thecontext of data being received from the host device in 8 Kbits in FIG.9, the same advantages are obtained in the case of receiving data inanother power-of-two number of bits.

In addition, the redundant data that is added to the binary data storedin the binary memory region 1 b, as described in the above embodiment,may be stored directly in the multi-value memory region 1 b and used forerror correction of multi-value data. Alternatively, the redundant dataadded to the binary data may be used for error correction of the binarydata, while additional redundant data may be generated and added formulti-value data at the ECC circuit.

Third Embodiment

Referring now to FIG. 10, a third embodiment of the present inventionwill be described below. According to this embodiment, the entireconfiguration of the semiconductor memory system is substantially thesame as the first embodiment (see FIGS. 1 to 6). This embodiment alsohas the same configuration as the second embodiment in that datasupplied from the external host device in a unit of a power-of-twonumber of bits is first written to the binary memory region 1 b, andthen converted into the three pages of data, which in turn are rewrittento the multi-value memory region 1 a.

However, the third embodiment is different from the second embodiment inthat 8 Kbits of effective data transferred from the host device,redundant data and management flags are stored in the binary memoryregion 1 b-1, and then some (or all) of the next 8 Kbits of datatransferred are stored in the residual region of the binary memoryregion 1 b-1. Hereinbelow, as illustrated in FIG. 10, residual portionsare also utilized effectively, rather than utilizing one binary memoryregion 1 b-i (i=1, 2, 3, . . . ) for every unit of data transferred fromthe host device. Then, when 32 Kbits of effective data, whichcorresponds to data for the three pages (LOWER, MIDDLE, UPPER) is storedin the binary memory regions 1 b-1 to 1 b-3, data transfer to themulti-value memory region 1 a is performed thereafter as described inthe second embodiment. With this scheme, effective use of the storageregions of the binary memory regions 1 b-1 to 1 b-3 is available,without leaving redundant storage regions.

Fourth Embodiment

Referring now to FIGS. 11 and 12, a fourth embodiment of the presentinvention will be described below. According to this embodiment, theentire configuration of the semiconductor memory system is substantiallythe same as the first embodiment (see FIGS. 1 to 6). In addition, thisembodiment also has the same configuration as the second and thirdembodiments in that data supplied from the external host device in aunit of power-of-two number of bits is first written to the binarymemory region 1 b, and then converted into the three pages of data,which in turn are rewritten to the multi-value memory region 1 a.

However, this embodiment is different from the above-mentionedembodiments in that data stored in the binary memory regions 1 b-1 to 1b-4 is once read out to the buffer RAM 26, then rearranged on the bufferRAM 26, and further stored in the multi-value memory region 1 a, withredundant data for multi-value being added thereto. The data stored inone binary memory region 1 b-i is separately stored in all of the threepages, UPPER, MIDDLE, and LOWER. It should be readily apparent thatwhile data is written to the binary memory regions 1 b-1 to 1 b-4 in asimilar way to the second embodiment in FIG. 11, it might also bewritten in a similar way to the third embodiment as illustrated in FIG.12.

[Others]

While embodiments of the present invention have been described, thepresent invention is not intended to be limited to the disclosedembodiments, and various other changes, additions or the like may bemade thereto without departing from the spirit of the invention. Forexample, while the description is made in the context of 3 bits of databeing stored in one memory cell in the above-described embodiments, thepresent invention is not so limited and may be applicable to otherimplementations where N bits of data (N is a natural number more than 2,other than a power-of-two) is stored in one memory cell.

In addition, the above embodiments are configured so that when apower-of-two number of bits of data are to be written from the outsideas a unit of data, they are once stored in the binary memory region 1 bwithin the memory cell array in unit of data before transferred to themulti-value memory region 1 a. The present invention, however, is not solimited and may, for example, directly write data to the multi-valuememory region 1 a. In addition, such a configuration may be employedwhere the memory cell array includes a plurality of memory chips, themulti-value memory region 1 a includes some of the plurality of chips,and the binary memory region 1 b includes others.

1. A semiconductor memory system comprising: a memory cell array havinga plurality of memory cells arranged therein, the plurality of memorycells capable of storing N bits of information in each memory cell(where N is a natural number more than 3, other than a power of two); acontrol circuit configured to control read, write, and erase operationson the memory cell array; and an ECC circuit configured to correct dataread from the memory cell array, based on redundant data, the memorycells that share one of word lines and can be written or read at a timebeing configured to store multiple pages of data therein, a total amountof data stored in the multiple pages being set to a power-of-two numberof bits, and the redundant data being stored in a residual portion ofthe multiple pages.
 2. The semiconductor memory system according toclaim 1, wherein the memory cell array comprises: a binary memory regionconfigured to store 1 bit of information in one of the memory cells; anda multi-value memory region formed to store the N bits of information inone of the memory cells, and the control circuit receives from outsidedata that is to be written in the memory cell array, the data beingsupplied from outside in a unit of data with a power-of-two number ofbits, stores the data in the binary memory region, and then sequentiallytransfers the data stored in the binary memory region to the multi-valuememory region.
 3. The semiconductor memory system according to claim 2,wherein the control circuit stores the unit of data with thepower-of-two number of bits separately in all of the pages in themulti-value memory region.
 4. The semiconductor memory system accordingto claim 3, wherein the binary memory region has a unit storage regionhaving a capacity larger than the unit of data with a power-of-twonumber of bits; and the control circuit stores the unit of data in theunit storage region, and, if the unit storage region involves anyresidual region, the control circuit stores in that residual region atleast a part of data in another unit of data to be supplied next.
 5. Thesemiconductor memory system according to claim 2, wherein the binarymemory region has a unit storage region having a capacity larger thanthe unit of data with a power-of-two number of bits; and the controlcircuit stores the unit of data in the unit storage region, and, if theunit storage region involves any residual region, the control circuitstores in that residual region at least a part of data in another unitof data to be supplied next.
 6. The semiconductor memory systemaccording to claim 2, wherein the redundant data added to the binarymemory region is used for error correction of multi-value data stored inthe multi-value memory region.
 7. The semiconductor memory systemaccording to claim 2, wherein the redundant data added to the binarymemory region is used for error correction of binary data.
 8. Thesemiconductor memory system according to claim 2, wherein the memorycell array includes a plurality of memory chips, each of the memorychips having the plurality of memory cells arranged therein; the binarymemory region includes some of the memory chips; and the multi-valuememory region includes others of the memory chips.
 9. The semiconductormemory system according to claim 1, wherein one of the multiple pagesstore data with a first number of bits, the first number being differentfrom a power-of-two.
 10. The semiconductor memory system according toclaim 1, wherein N=3, and the residual portion of the multiple pages isset to 3α Kbits+1 Kbits (where α is a natural number).
 11. Thesemiconductor memory system according to claim 10, wherein the redundantdata is set to have an amount of data larger than 1 Kbits.
 12. Thesemiconductor memory system according to claim 1, wherein each of theplurality of memory cells comprises: a substrate; a first diffusionlayer provided on the substrate and functioning as a source and a drain;a floating gate formed on the substrate via a first insulation layer;and a first control gate formed on the floating gate via a secondinsulation layer.
 13. The semiconductor memory system according to claim1, wherein the memory cell array comprises: a first selection gatetransistor having its one end connected to one end of each of the memorycells connected in series; and a second selection gate transistor havingits one end connected to the other end of each of the memory cellsconnected in series.
 14. The semiconductor memory system according toclaim 13, wherein each of the first selection gate transistor and thesecond selection gate transistor comprises: a substrate; a firstdiffusion layer provided on the substrate and functioning as a sourceand a drain; and a first control gate provided on the substrate via afirst insulation layer.
 15. The semiconductor memory system according toclaim 1, wherein the control circuit sets respective ones of the memorycells that are selected in write operation to have any of 2^(N)different threshold voltages, sets respective ones of the word linesselected in read operation to have respective read voltages between thethreshold voltages, and sets respective ones of the word linesnon-selected in read operation to have a voltage greater than thehighest one of the threshold voltages.
 16. The semiconductor memorysystem according to claim 15, wherein when checking a completion ofwrite operation, the control circuit sets the selected word lines tohave a voltage greater than the respective read voltages positionedbetween the threshold voltages.
 17. A semiconductor memory systemcomprising: a memory cell array having a plurality of memory cellsarranged therein, the plurality of memory cells capable of storing Nbits of information in each memory cell (where N is a natural numbermore than 3, other than a power of two); and a control circuitconfigured to control read, write, and erase operations on the memorycell array, the memory cell array comprising: a binary memory regionconfigured to store 1 bit of information in one of the memory cells; anda multi-value memory region formed to store the N bits of information inone of the memory cells, the control circuit being operative to store inthe binary memory region data supplied from outside in a unit of datawith a power-of-two number of bits to be written to the memory cellarray, and then sequentially transfer the data stored in the binarymemory region to the multi-value memory region; the memory cells thatshare one of word lines and can be written or read at a time beingconfigured to store multiple pages of data therein; and a total amountof data stored in the multiple pages being set to a power-of-two numberof bits, and the redundant data being stored in a residual portion ofthe multiple pages.
 18. The semiconductor memory system according toclaim 17, wherein the control circuit stores the unit of data with thepower-of-two number of bits separately in all of the pages in themulti-value memory region.
 19. The semiconductor memory system accordingto claim 17, wherein one of the multiple pages store data with a firstnumber of bits, the first number being different from a power-of-two.20. The semiconductor memory system according to claim 17, wherein thememory cell array includes a plurality of memory chips, each of thememory chips having the plurality of memory cells arranged therein; thebinary memory region includes some of the memory chips; and themulti-value memory region includes others of the memory chips.